1. Field of the Invention
The present invention relates to a semiconductor device for use as a power switching element, and more particularly to a semiconductor device having a super junction structure and a manufacturing method of the same.
2. Description of the Related Art
Recent years have seen a growing demand for thickness and weight reduction of electronic equipment as typified by liquid crystal, plasma and organic EL (Electro-Luminescence) television sets. This has led to a greater demand for size reduction and higher performance of power equipment. As a result, much effort has been put into providing improved performance to power semiconductor elements, and vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) in particular. Such performance improvements include higher withstand voltage, larger current handling capability, lower losses, higher speed and higher breakdown resistance.
The ON resistance and withstand voltage of a vertical MOSFET depends largely on the impurity concentration of its conduction layer, i.e., a first conductivity type region of the MOSFET such as an n-type semiconductor region. The impurity concentration of the conduction layer must be increased to reduce the ON resistance. However, the impurity concentration cannot be increased beyond a given level to achieve a desired withstand voltage. That is, for a vertical MOSFET, the ON resistance and withstand voltage are in a tradeoff relationship.
A known solution to improve this is a so-called super junction structure in which a semiconductor region of a second conductivity type such as p type and a semiconductor region of the first conductivity type such as n type are arranged alternately or in a striped pattern in the region where withstand voltage is demanded. When a vertical MOSFET having a super junction structure is ON, a current flows through the first conductivity type conduction layer. When the MOSFET is OFF, the second conductivity type semiconductor region and the N region of the first conductivity type conduction layer become completely depleted. Thus, the super junction structure provides a demanded withstand voltage.
For example, the following three methods are known for manufacturing the super junction structure:
(1) Introduce n- and p-type impurities separately into a Si epitaxial layer through ion implantation and stack one epitaxial structure above another a plurality of times.
(2) Form trenches in a thick epitaxial layer and provide an impurity layer on the side surfaces of the trenches by diffusion or other means so as to embed an insulating or non-conductive substance in the trenches.
(3) Form trenches in a thick epitaxial layer and fill the trenches with a silicon epitaxial layer containing an impurity.
The third method may be able to provide a super junction structure with a high integration by a small number of process steps. For example, it has been proposed to form a super junction region by introducing a new idea to the crystal plane orientation of the wafer and to the method of forming a super junction structure (refer, for example, to Japanese Patent Laid-Open No. 2007-173734).